Baud Rate Select Register
| SCKDV | SPI Clock Divider. This field contains the MSB 15 bits of the 16-bit SPI_CLK divider value. The LSB for SPI_CLK divider is always set to 0 and is unaffected by a write operation, which ensures the divider is always set to an even value. If this field is set to all 0s, the serial output clock (SPI_SCLK) is disabled. The frequency of the SPI_SCLK is derived from the following equation: FSPI_SCLK = FSPI_CLK/BAUDR Where BAUDR is any even value between 2 and 65534, and BAUDR = SCKDV x 2. For example, for FSPI_CLK = 3.6864 MHz and SCKDV = 1b’1: BAUDR = 2 and FSPI_SCLK= 3.6864/2 = 1.8432 MHz. For more information, see Section SPI Clock Ratios. |